In the information age, there is an increasing need to transmit large quantities of information among a multitude of different types of customer terminals. Also, large telecommunication switching systems are expected to switch many types of information in addition to voice. The data rates for these different types of terminals range from 1.2 kb/s (e.g. computer terminal) to 8000 kb/s (e.g. video). In order to communicate such a wide range of data rates, some prior art telecommunication systems have used a circuit switch for switching voice, a packet switch for switching bursty type data, and a video switch for switching video. However, a packet switch is only a partial solution for switching bursty type data because some applications have critical delay requirements that are difficult to guarantee with packet switches. Further, the use of these different types of switches adds to the cost and complexity of administrating a telecommunication system.
The switching architecture of a prior art telecommunication switching system for circuit switching voice and certain other types of data is illustrated in FIG. 1. This system is similar to the AT&T 5ESS Switching System described in the AT&T Technical Journal, Volume 64, July-August, 1985, No. 6, Part 2. Not shown in FIG. 1 is the control circuitry to perform the necessary control functions. As described in the AT&T Technical Journal data is communicated within this prior art system by time division multiplexing data into "channels" with each channel comprising one or more time slots. The time slots are grouped into "frames". In the illustrated system, there are 512 time slots per frame, and each time slot can communicate data at 64 kb/s. In principle, the illustrated system can be used for channels having data rates higher than 64 kb/s by assigning multiple time slots to each channel. Since, a time slot is the smallest allocatable unit of channel capacity, different numbers of time slots may be assigned to channels with different capacity requirements; however, the data rate of a channel cannot be less than the data rate of single channel.
There are four problems that make prior art switching systems impractical for channels with numerous time slots: (1) time slot accounting, (2) buffer storage requirements, (3) switching delays, and (4) data order integrity. The time slot accounting problem results because any combination of time slots may be allocated to any channel and each time slot requires individual processing during allocation. As more time slots are allocated to a channel, more memory space is required in a switching unit (e.g. a time multiplexer switch) to keep track of which time slots are allocated to the channel. Also, more time is required for a control algorithm to set up the channel. This additional channel setup time is an important consideration in a large switching unit such as the time multiplexer switch of the AT&T 5ESS Switching System.
The buffer storage problem results because prior art switching systems require sufficient buffer storage in each switching unit (e.g. time slot multiplexers, time slot demultiplexers, and time multiplexer switch) to store two frames of time slots. Hence, any channel that uses a large number of time slots consumes a proportionately large amount of buffer memory space. In addition, buffer memories of this type must have very fast access times even when 8 bits of data are included in each time slot. If the number of bits of data per time slot is reduced, the access time of these buffer memories proportionately increases.
The switching delay problem results because prior art switching systems introduce delay in multiples of a frame period. Normally, this delay is equal to five frame periods for a prior art switching system and is due to the need to fully buffer the frames at each input and output stage of each switching unit.
In most prior art switching systems, the data ordering problem requires consecutive time slots for a multi-time slot channel in order to guarantee that data will not be reordered as the data is transferred through various buffer storage units. The result is that information is received from these time slots at high burst rates and must be buffered so that the data can be transferred at a steady rate to a receiving terminal. Similarly, data received at a steady rate from the terminal must be buffered in order to be placed in the consecutive time slots.
Each of the above four problems is a function of the number of time slots allocated to a channel and is not a function of channel capacity. As long as sufficiently fast circuitry is available and the channel capacity equals an individual time slot, conventional time division switching principles can be used without the above problems becoming effective. If different channel capacities are required particularly for other than multiples of 64 kb/s, then the above problems become effective.
U.S. Pat. No. 4,855,996 discloses a small telecommunication switching system that solves the aforementioned data ordering problem but implements only one time division bus as illustrated in FIG. 1. Further, the buffer storage and switching delay problems never occur in such a small switching system because it has only one time division bus. Also, the time slot accounting problem is not solved by the disclosed method. (Note U.S. Pat. No. 4,855,996 refers to time slots as access times and to channels as time slots.) The time slot accounting problem is not solved by the disclosed method because each of the time slots requires a memory word in a central memory and must be individually assigned to a channel. To handle terminals transmitting at different data rates, this patent discloses a method that determines the number of time slots per frame and the number of time slots to be assigned to each channel for a specified data rate. In addition, the method determines the time slots for a given channel so that those time slots are evenly spaced throughout the frame.